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[VHDL-FPGA-Verilog] Lattice_Verilog

Description: 本文讨论了AR模型及线性预测的原理，在浮点型DSP TMS320C6713B上实现了语音信号线性预测系数(LPC)的提取，并利用LPC系数用Verilog语言实现了AR模型的Lattice结构。-This article discusses the AR model and the principle of linear prediction, in the floating-point DSP TMS320C6713B realize the voice signal on the linear prediction coefficient (LPC) of the extract, and the use of LPC coefficients using Verilog languages realize the AR model Lattice structure.
Platform: | Size: 14336 | Author: 万金油 | Hits:

[VHDL-FPGA-Verilog] CourseDesign

Description: 用Verilog实现一位原码浮点数乘法器，按照累加的方式，逐位相乘，再相加。-Verilog realization of an original code with floating point multiplier, in accordance with the cumulative way, bit by bit multiply, then add.
Platform: | Size: 245760 | Author: 李伟彬 | Hits:

[VHDL-FPGA-Verilog] fpufiles

Description: floating point adder mul and sub in verilog code
Platform: | Size: 19456 | Author: khosro raja | Hits:

[VHDL-FPGA-Verilog] canbus

Description: CAN总线的FPGA实现，用Verilog编写，代码完整，而且有很完善的测试代码，用ISE直接打开，学习FPGA进阶的好项目-CAN Bus FPGA, written with Verilog, code integrity, but also very good test code, using ISE directly open, a good project to learn advanced FPGA
Platform: | Size: 863232 | Author: 张小琛 | Hits:

[VHDL-FPGA-Verilog] fpu_div

Description: verilog code floating point division
Platform: | Size: 2048 | Author: Nikhil | Hits:

[VHDL-FPGA-Verilog] FPU

Description: Verilog HDL code for implementation of double floating point architecture. Program takes care of diffent exceptions like overflow, underflow, NaN etc
Platform: | Size: 696320 | Author: Ruchi | Hits:

[VHDL-FPGA-Verilog] mult

Description: 32位浮点乘法器的源代码，用verilog来实现的-32-bit floating point multiplier source code to achieve with verilog
Platform: | Size: 2048 | Author: yolin | Hits:

[VHDL-FPGA-Verilog] emiraga-ieee754-verilog-b7a63aa

Description: IEEE 754 floating point
Platform: | Size: 17408 | Author: Joe | Hits:

[VHDL-FPGA-Verilog] divider

Description: verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。-verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.
Platform: | Size: 2048 | Author: 韩冰 | Hits:

[VHDL-FPGA-Verilog] Floating-Point-Multiplier-in-Verilog

Description: Floating Point Multiplier in Verilog
Platform: | Size: 64512 | Author: Khalid Nawaz Khan | Hits:

[VHDL-FPGA-Verilog] a-floating-point-adder

Description: 一个浮点加法器，verilog描述，数据格式：高14位为尾数，低四位位指数（带符号数运算）-A floating point adder Verilog description
Platform: | Size: 2048 | Author: 张松 | Hits:

[LabView] Verilog

Description: design floating point unit
Platform: | Size: 998400 | Author: Nam | Hits:

[VHDL-FPGA-Verilog] floating-point-multip

Description: verilog code for floating point multiplier
Platform: | Size: 51200 | Author: rajesh | Hits:

[VHDL-FPGA-Verilog] adder

Description: 能够实现单精度浮点加法运算。输入引脚有：第一运算数，第二运算数，复位信号，时钟信号。输出信号有：运算结果，运算完成标志。(To achieve a single precision floating-point addition operations)
Platform: | Size: 5219328 | Author: 无聊人 | Hits:

[VHDL-FPGA-Verilog] 数字信号处理的FPGA实现-第三版-verilog源程序

Description: 数字信号处理的FPGA实现, 包括了FPGA基础知识，浮点运算，信号处理的FIR FFT等，附录包含源代码(Digital signal processing FPGA implementation, including the basic knowledge of FPGA, floating point operations, signal processing FIR, FFT, etc., the appendix contains the source code)
Platform: | Size: 4568064 | Author: btty | Hits:

[VHDL-FPGA-Verilog] float_2_int.v

Description: 最全的，最简单，32位浮点数转整数，32位整数转浮点数，直接可以移植，已经测试过好用。(The most complete, the simplest, 32 bit floating-point integer, 32 integer floating point number, can be directly transplanted, has been tested, easy to use.)
Platform: | Size: 1024 | Author: 那里的星空 | Hits:

[VHDL-FPGA-Verilog] eetop.cn_利用FPGA实现浮点运算的verilog代码

Description: 计算机里整数和小数形式就是按普通格式进行存储，例如1024、3.1415926等等，这个没什么特点，但是这样的数精度不高，表达也不够全面，为了能够有一种数的通用表示法，就发明了浮点数。 浮点数的表示形式有点像科学计数法（*.*****×10^***），它的表示形式是0.*****×10^***，在计算机中的形式为 .***** e ±***），其中前面的星号代表定点小数，也就是整数部分为0的纯小数，后面的指数部分是定点整数。利用这样的形式就能表示出任意一个整数和小数，例如1024就能表示成0.1024×10^4，也就是 .1024e+004，3.1415926就能表示成0.31415926×10^1，也就是 .31415926e+001，这就是浮点数。浮点数进行的运算就是浮点运算。 浮点运算比常规运算更复杂，因此计算机进行浮点运算速度要比进行常规运算慢得多。(Floating point representation is a bit like scientific notation (*.***** * 10^***), its representation is 0.***** * 10^*** in the computer in the form of.***** e +, * * *) in front of the asterisk represents fixed-point decimal, which is part of the 0 pure decimal integer index, part of the back is a fixed integer. In this way, any integer and decimal can be expressed. For example, 1024 can be expressed as 0.1024 * 10^4, that is,.1024e+004, 3.1415926 can be expressed as 0.31415926 * 10^1, that is.31415926e+001, that is the floating point number. The operation of floating-point numbers is floating point operation.)
Platform: | Size: 130048 | Author: 哒啦啦啦 | Hits:

[VHDL-FPGA-Verilog] iir_2n_ip_float_demo

Description: 使用altera提供的ip核，实现了浮点数运算的2阶iir滤波器，结果与matlab运算结果相同。(Using the IP core provided by Altera, the 2 order IIR filter of floating point operation is implemented, and the result is the same as that of MATLAB operation.)
Platform: | Size: 48926720 | Author: 小天夫斯基 | Hits:

[VHDL-FPGA-Verilog] float_multi_module

Description: float_multi_module实现了单精度浮点乘法运算(Float_multi_module implements single precision floating point multiplication.)
Platform: | Size: 1024 | Author: sisuozheweilai | Hits:

[Other] 基于FPGA的单精度浮点数乘法器设计

Description: 《基于FPGA的单精度浮点数乘法器设计》详细介绍了按照IEEE754标准在FPGA上实现单精度浮点加减乘除的方法(The design of single precision floating point multiplier based on FPGA introduces in detail the way of realizing single precision floating point addition, subtraction and multiplication and division based on IEEE754 standard on FPGA.)
Platform: | Size: 2432000 | Author: sisuozheweilai | Hits:
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